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W631GG6KB
Previous clock frequency
New clock frequency
T0
T1
T2
Ta0
Tb0
Tc0
Tc1
Td0
Td1
Te0
Te1
CK#
CK
t CH
t CL
t CH b
t CL b
t CH b
t CL b
t CH b
t CL b
t CK
t CKSRE
t CK b
t CKSRX
t CK b
t CK b
t CKE
CKE
t IH
t IS
t CPDED
t IH
t IS
Command
NOP
NOP
NOP
NOP
NOP
MRS
NOP
VALID
Address
DLL Reset
VALID
t AOFPD / t AOF
t XP
t IH
t IS
ODT
DQS, DQS#
DQ
High-Z
High-Z
DM
t DLLK
Enter PRECHARGE
Power-Down Mode
Frequency
Change
Exit PRECHARGE
Power-Down Mode
TIME BREAK
DON'T CARE
Notes:
1. Applicable for both SLOW EXIT and FAST EXIT Precharge Power-down.
2. t AOFPD and t AOF must be satisfied and outputs High-Z prior to T1; refer to ODT timing section for exact requirements.
3. If the Rtt_Nom feature was enabled in the mode register prior to entering Precharge power down mode, the ODT signal must
continuously be registered LOW ensuring R TT is in an off state, as shown in Figure 9. If the Rtt_Nom feature was disabled in
the mode register prior to entering Precharge power down mode, R TT will remain in the off state. The ODT signal can be
registered either LOW or HIGH in this case.
Figure 12 – Change Frequency during Precharge Power-down
Publication Release Date: Dec. 09, 2013
Revision A05
- 29 -
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